1. Field of the Invention
The present invention generally relates to dynamic memories (DRAMs) which are volatile memories requiring refreshment of the cells to maintain the information that they contain. The present invention more specifically applies to battery-supplied mobile systems, for example, cell phones or cellular terminals of 3G/EGPRS/GSM type.
2. Discussion of the Related Art
DRAMs are generally formed of an array of memory cells with which are associated addressing and input/output circuits as well as a refreshment circuit. The refreshment circuit is used to periodically address all the memory cells to preserve the information that they contain.
In a cell phone application, such DRAMs are generally used in circuits (screen, camera, GSM—A-GPS assisted satellite position finding system, . . . ) peripheral to the basic telephony circuit (modem).
FIG. 1 is a schematic block diagram illustrating a conventional embodiment of a simplified architecture of the digital circuits of a GSM-type cell phone. For simplification, only the digital circuits have been shown, although the telephone of course comprises radio-frequency transceiver circuits to communicate with the GSM network and its stations.
The main element of the telephone is a digital baseband processor (DBP) circuit 1 forming the telephony circuit and comprising the modulation-demodulation elements necessary for communications with the GSM network. Inside of the telephone, circuit 1 is connected by one or several data exchange, address, and control and supply signal buses 2 to the other mobile phone elements. Among the circuits connected to buses 2, there is a power management circuit 3 (PW), application circuits 8 (CAMERA), for example, for a video or photographic camera, satellite position finding circuits 9 (A-GPS), a unit 10 (for example, an arithmetical and logic unit—UART) of asynchronous communication with the outside (for example, with a PC), and different memories, for example, a non-volatile memory (ROM), a DRAM 5, a flash-type memory 6 (FLASH), and a SRAM 7. Other components are present in the telephone, especially to manage the elements of keyboard type, etc.
The present invention more specifically applies to circuit 1 forming the telephony circuit which, unlike the other application circuits contained in the telephone, must keep on operating in stand-by mode of the mobile phone, especially to periodically communicate with the GSM network and be woken up on reception of an incoming call.
FIG. 2 very schematically shows in the form of blocks an example of a conventional architecture of telephony circuit 1 of a GSM terminal. All the elements illustrated in FIG. 2 are integrated on a same chip.
Circuit 1 essentially comprises:
an external memory controller 11 for communicating with bus 2;
a microprocessor 12 (ARM926EJ-S Core) associated with two cache memory elements 13 (I Cache) and 14 (D Cache);
a circuit 15 (ARM peripherals and Modem) containing peripherals of the microprocessor as well as a modem for communicating with analog radio-frequency transceiver circuits (not shown);
a SRAM 18;
a boot ROM; and
an internal bus system 16 (AMBA bus system) dedicated to microprocessor 12 and to which are especially connected circuits 11, 12, 13, 14, 15, 17, and 18.
Most often, a telephony circuit also comprises:
a signal processor (DSP) 21 (ST122 Core) associated with an SRAM-type data memory 22;
a program memory extension circuit 23 comprising a ROM circuit 24 (Program ROM) for containing programs dedicated to processor 21, an SRAM circuit 25 (Patch RAM) for containing updates of these programs during the circuit lifetime, and a cache memory circuit 26 dedicated to processor 21; and
a bus management system 20 (DSP bus system) to which are connected the circuits dedicated to processor 21 and which is itself connected to main bus 16.
For simplification, the different connections between the elements inside of circuit 1 have not been shown and only the connection to buses 2 from controller 11 has been illustrated.
The operation of such a telephony circuit is known and does not need to be further detailed for the discussion of the present invention.
Conventional telephony circuits suffer from several disadvantages linked to the used memory circuits. In particular, on the side of signal processor 21, the use of a ROM 24 to contain the programs adversely affects the flexibility of the signal processor and the necessary updates of its content.
It has already been devised to replace this memory with flash memory, but flash memories have the disadvantage of not being programmable on the fly, that is, by communications with the GSM network to modify applications in the telephone lifetime.
As for SRAMs, they pose problems of size and power consumption during their operation. It is accordingly conventionally attempted to minimize the size of circuits 18 and 25 which are SRAMs.
The use of SRAMs or ROMs is linked to their non-volatile character generating no power consumption to keep the information in stand-by periods of the telephone.
On the size of microprocessor 12, the presence of an SRAM circuit 18 adversely affects the system size and power consumption.
Further, the capacities of the memories required by mobile phones and more generally GSM terminals become greater and greater. This capacity increase conventionally performed by means of SRAMs is not desirable.
Such problems are essentially present for telephony circuit 1. Indeed, the other GSM terminal circuits are less sensitive since they are not active in stand-by periods of the telephone.
The use of DRAMs would be a solution. However, such memories are volatile and require permanent refreshment to preserve the information that they contain. They thus have been discarded up to now due to the large power consumption required by such a refreshment.
FIG. 3 schematically shows in the form of blocks an example of a conventional architecture of a DRAM circuit 40. Such a circuit essentially comprises an array network 41 (MEM ARRAY) of memory cells connected by input/output circuits 42 (I/O DRIVERS) to an input data bus 43 (DATA IN) and to an output data bus 44 (DATA OUT). Circuit 40 comprises a address bus input 45 (ADD) connected, by a selection multiplexer 55, to a control interface 46 (CTRL INTERF). A second input of the multiplexer receives addresses automatically generated by a refreshment controller 48 (NRC) periodically generating all the addresses of network 41 to preserve the information that they contain. Circuit 48 receives a clock signal CKIN from the outside of circuit 40 which is also directly sent to control interface 46. Selector 55 is controlled by a signal originating from a control circuit not shown of the memory. Interface 46 provides addresses to an address decoder 47 (ADD ROW DEC) for selecting the addressed memory cells in network 41 and to a precharge of the bit lines. Finally, circuit 40 integrates a linear regulator 49 receiving a supply voltage Vdd from the outside and providing a regulated supply voltage Vc, among others, to one of the electrodes (in practice, the common electrode) of all the capacitive elements of network 41. For simplification, FIG. 4 only shows the elements and connections useful for the refreshment. Memory 40 of course comprises other circuits used for the data transfer and the user mode as well as a general control circuit. Further, circuit 40 may exchange other signals with the outside, for example, over a control bus.
The architecture of FIG. 4 for example corresponds to that of memory 5 (FIG. 1).
The integration of a memory such as illustrated in FIG. 3 in a telephony circuit is incompatible with the low power consumption needs of this circuit in standby period.
Indeed, when the mobile phone is at standby, the telephone processor only operates with limited functions and under a reduced supply voltage. These limited functions especially are the periodic interrogation of the base stations of the GSM network to detect a possible incoming call as well as a circuit waking function by the user himself. At standby, the internal circuits of generation of a high-frequency clock (several tens of MHz) for the operation of the processors and the refreshment of the DRAMs (signal CKIN) are deactivated.
Now, the memory cell refreshment requires on the one hand a clock frequency and on the other hand a sufficient supply voltage. The greater the memory capacity, the higher the clock frequency must be to enable a refreshment compatible with the cell retention capacity. Typically, the retention time of a DRAM is of several tens of milliseconds.
Another difficulty is that the supply voltage provided to the telephony circuit is different in the standby mode and in the active mode. Typically, in GSM-type telephony circuits, this voltage falls from on the order of 1.2 volt in operation to approximately 0.95 volt at standby.
Such constraints result in that conventional DRAMs are unadapted.